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general description the MAX12553 is a 3.3v, 14-bit, 65msps analog-to-digital converter (adc) featuring a fully differential wideband track-and-hold (t/h) input amplifier, driving a low-noise internal quantizer. the analog input stage accepts single- ended or differential signals. the MAX12553 is optimized for low-power, small size, and high dynamic perfor- mance. excellent dynamic performance is maintained from baseband to input frequencies of 175mhz and beyond, making the MAX12553 ideal for intermediate- frequency (if) sampling applications. powered from a single 3.15v to 3.60v supply, the MAX12553 consumes only 363mw while delivering a typical signal-to-noise (snr) performance of 71db at an input frequency of 175mhz. in addition to low oper- ating power, the MAX12553 features a 150? power- down mode to conserve power during idle periods. a flexible reference structure allows the MAX12553 to use the internal 2.048v bandgap reference or accept an externally applied reference. the reference structure allows the full-scale analog input range to be adjusted from ?.35v to ?.10v. the MAX12553 provides a com- mon-mode reference to simplify design and reduce exter- nal component count in differential analog input circuits. the MAX12553 supports both a single-ended and dif- ferential input clock drive. wide variations in the clock duty cycle are compensated with the adc? internal duty-cycle equalizer (dce). adc conversion results are available through a 14-bit, parallel, cmos-compatible output bus. the digital out- put format is pin selectable to be either two? comple- ment or gray code. a data-valid indicator eliminates external components that are normally required for reli- able digital interfacing. a separate digital power input accepts a wide 1.7v to 3.6v supply, allowing the MAX12553 to interface with various logic levels. the MAX12553 is available in a 6mm x 6mm x 0.8mm, 40-pin thin qfn package with exposed paddle (ep), and is specified for the extended industrial (-40? to +85?) temperature range. see the pin-compatible versions table for a complete family of 14-bit and 12-bit high-speed adcs. applications if and baseband communication receivers cellular, point-to-point microwave, hfc, wlan ultrasound and medical imaging portable instrumentation low-power data acquisition features ? direct if sampling up to 400mhz ? excellent dynamic performance 74.0db/71db snr at f in = 3mhz/175mhz 90.6dbc/80.7dbc sfdr at f in = 3mhz/175mhz ? low noise floor: -76dbfs ? 3.3v low-power operation 337mw (single-ended clock mode) 363mw (differential clock mode) 150? (power-down mode) ? fully differential or single-ended analog input ? adjustable full-scale analog input range: ?.35v to ?.10v ? common-mode reference ? cmos-compatible outputs in two? complement or gray code ? data-valid indicator simplifies digital interface ? data out-of-range indicator ? miniature, 40-pin thin qfn package with exposed paddle ? evaluation kit available (order max12555evkit) MAX12553 14-bit, 65msps, 3.3v adc ________________________________________________________________ maxim integrated products 1 ordering information 19-3343; rev 0; 8/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package pkg code MAX12553etl -40 c to +85 c 40 thin qfn (6mm x 6mm x 0.8mm) t4066-3 pin-compatible versions part sampling rate (msps) resolution (bits) target application MAX12553 65 14 if/baseband max1209 80 12 if max1211 65 12 if max1208 80 12 baseband max1207 65 12 baseband max1206 40 12 baseband pin configuration appears at end of data sheet.
MAX12553 14-bit, 65msps, 3.3v adc 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), v in = -0.5dbfs, clktyp = high, dce = high, pd = low, g/ t = low, f clk = 65mhz (50% duty cycle), t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ...........................................................-0.3v to +3.6v ov dd to gnd........-0.3v to the lower of (v dd + 0.3v) and +3.6v inp, inn to gnd ...-0.3v to the lower of (v dd + 0.3v) and +3.6v refin, refout, refp, refn, com to gnd................-0.3v to the l ower of (v dd + 0.3v) and +3.6v clkp, clkn, clktyp, g/ t , dce, pd to gnd ........-0.3v to the lower of (v dd + 0.3v) and +3.6v d13?0, dav, dor to gnd....................-0.3v to (ov dd + 0.3v) continuous power dissipation (t a = +70?) 40-pin thin qfn 6mm x 6mm x 0.8mm (derated 26.3mw/? above +70?)........................2105.3mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering 10s) ..................................+300? parameter symbol conditions min typ max units dc accuracy (note 2) resolution 14 bits integral nonlinearity inl f in = 3mhz (note 5) ?.4 4.2 lsb differential nonlinearity dnl f in = 3mhz, no missing codes over temperature (note 3) ?.5 1.0 lsb offset error v refin = 2.048v ?.1 0.55 %fs gain error v refin = 2.048v ?.5 ?.9 %fs analog input (inp, inn) differential input voltage range v diff differential or single-ended inputs 1.024 v common-mode input voltage v dd /2 v c par fixed capacitance to ground 2 input capacitance (figure 3) c sample switched capacitance 4.5 pf conversion rate maximum clock frequency f clk 65 mhz minimum clock frequency 5 mhz data latency figure 6 8.5 clock cycles dynamic characteristics (differential inputs, note 2) small-signal noise floor ssnf input at less than -35dbfs -76.0 dbfs f in = 3mhz at -0.5dbfs (note 8) 69.3 74.0 f in = 32.5mhz at -0.5dbfs 73.9 f in = 70mhz at -0.5dbfs 73.4 signal-to-noise ratio snr f in = 175mhz at -0.5dbfs (notes 7, 8) 68.0 71.0 db f in = 3mhz at -0.5dbfs (note 8) 69.2 73.9 f in = 32.5mhz at -0.5dbfs 73.1 f in = 70mhz at -0.5dbfs 73.1 signal-to-noise and distortion sinad f in = 175mhz at -0.5dbfs (notes 7, 8) 67.6 70.0 db
MAX12553 14-bit, 65msps, 3.3v adc _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), v in = -0.5dbfs, clktyp = high, dce = high, pd = low, g/ t = low, f clk = 65mhz (50% duty cycle), t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units f in = 3mhz at -0.5dbfs 79.8 90.6 f in = 32.5mhz at -0.5dbfs 84.0 f in = 70mhz at -0.5dbfs 87.8 spurious-free dynamic range sfdr f in = 175mhz at -0.5dbfs (note 7) 75.9 80.7 dbc f in = 3mhz at -0.5dbfs -90.6 -80.2 f in = 32.5mhz at -0.5dbfs -81.0 f in = 70mhz at -0.5dbfs -85.4 total harmonic distortion thd f in = 175mhz at -0.5dbfs -78.9 -71.3 dbc f in = 3mhz at -0.5dbfs -99 f in = 32.5mhz at -0.5dbfs -91 f in = 70mhz at -0.5dbfs -92 second harmonic hd2 f in = 175mhz at -0.5dbfs -81 dbc f in = 3mhz at -0.5dbfs -94 f in = 32.5mhz at -0.5dbfs -84 f in = 70mhz at -0.5dbfs -88 third harmonic hd3 f in = 175mhz at -0.5dbfs -86 dbc f in1 = 68.5mhz at -7dbfs f in2 = 71.5mhz at -7dbfs -87 intermodulation distortion imd f in1 = 172.5mhz at -7dbfs f in2 = 177.5mhz at -7dbfs -80 dbc f in1 = 68.5mhz at -7dbfs f in2 = 71.5mhz at -7dbfs -91 third-order intermodulation im3 f in1 = 172.5mhz at -7dbfs f in2 = 177.5mhz at -7dbfs -83 dbc f in1 = 68.5mhz at -7dbfs f in2 = 71.5mhz at -7dbfs 90 two-tone spurious-free dynamic range sfdr tt f in1 = 172.5mhz at -7dbfs f in2 = 177.5mhz at -7dbfs 81 dbc aperture delay t ad figure 4 1.2 ns aperture jitter t aj figure 4 <0.2 ps rms output noise n out inp = inn = com 0.95 lsb rms overdrive recovery time ?0% beyond full scale 1 clock cycles
MAX12553 14-bit, 65msps, 3.3v adc 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), v in = -0.5dbfs, clktyp = high, dce = high, pd = low, g/ t = low, f clk = 65mhz (50% duty cycle), t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units internal reference (refin = refout; v refp , v refn , and v com are generated internally) refout output voltage v refout 2.002 2.048 2.066 v com output voltage v com v dd /2 1.65 v differential reference output voltage v ref v ref = v refp - v refn = v refin x 3/4 1.536 v refout load regulation 35 mv/ma refout temperature coefficient tc ref +50 ppm/? short to v dd ?inking 0.24 refout short-circuit current short to gndsourcing 2.1 ma b u f f er ed ext er n a l r ef er en c e ( r ef in d r iv e n e x t e r n a lly ; v r ef in = 2.0 4 8 v, v r ef p , v r ef n , a n d v c om a r e g e n e r a t e d in t e r n a lly ) refin input voltage v refin 2.048 v refp output voltage v refp (v dd /2) + (v refin x 3/8) 2.418 v refn output voltage v refn (v dd /2) - (v refin x 3/8) 0.882 v com output voltage v com v dd /2 1.60 1.65 1.70 v differential reference output voltage v ref v ref = v refp - v refn = v refin x 3/4 1.463 1.536 1.601 v differential reference temperature coefficient ?5 ppm/? refin input resistance >50 m ? unbuffered external reference (refin = gnd; v refp , v refn , and v com are applied externally) com input voltage v com v dd /2 1.65 v refp input voltage v refp - v com 0.768 v refn input voltage v refn - v com -0.768 v differential reference input voltage v ref v ref = v refp - v refn = v refin x 3/4 1.536 v refp sink current i refp v refp = 2.418v 1 ma refn source current i refn v refn = 0.882v 0.7 ma com sink current i com 0.7 ma refp, refn capacitance 13 pf com capacitance 6pf clock inputs (clkp, clkn) single-ended input high threshold v ih clktyp = gnd, clkn = gnd 0.8 x v dd v single-ended input low threshold v il clktyp = gnd, clkn = gnd 0.2 x v dd v differential input voltage swing clktyp = high 1.4 v p-p differential input common-mode voltage clktyp = high v dd / 2 v
MAX12553 14-bit, 65msps, 3.3v adc _______________________________________________________________________________________ 5 electrical characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), v in = -0.5dbfs, clktyp = high, dce = high, pd = low, g/ t = low, f clk = 65mhz (50% duty cycle), t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units input resistance r clk figure 5 5 k ? input capacitance c clk 2pf digital inputs (clktyp, g/t, pd) input high threshold v ih 0.8 x ov dd v input low threshold v il 0.2 x ov dd v v ih = ov dd 5 input leakage current v il = 0 5 ? input capacitance c din 5pf digital outputs (d13?0, dav, dor) d13?0, dor, i sink = 200? 0.2 output voltage low v ol dav, i sink = 600? 0.2 v d13?0, dor, i source = 200? ov dd - 0.2 output voltage high v oh dav, i source = 600? ov dd - 0.2 v tri-state leakage current i leak (note 4) ? ? d13?0, dor tri-state output capacitance c out (note 4) 3 pf dav tri-state output capacitance c dav (note 4) 6 pf power requirements analog supply voltage v dd 3.15 3.3 3.60 v digital output supply voltage ov dd 1.7 2.0 v dd + 0.3v v normal operating mode, f in = 175mhz at -0.5dbfs, clktyp = gnd, single-ended clock 102 normal operating mode, f in = 175mhz at -0.5dbfs, clktyp = ov dd, differential clock 110 123 analog supply current i vdd power-down mode clock idle, pd = ov dd 0.045 ma
MAX12553 14-bit, 65msps, 3.3v adc 6 _______________________________________________________________________________________ note 1: specifications +25? guaranteed by production test; <+25? guaranteed by design and characterization. note 2: see definitions in the parameter definitions section at the end of this data sheet. note 3: specifications guaranteed by design and characterization. devices tested for performance during production test. note 4: during power-down, d13?0, dor, and dav are high impedance. note 5: guaranteed by design and characterization. note 6: digital outputs settle to v ih or v il . note 7: due to test-equipment-jitter limitations at 175mhz, 0.15% of the spectrum on each side of the fundamental is excluded from the spectral analysis. note 8: limit specifications include performance degradations due to a production test socket. performance is improved when the MAX12553 is soldered directly to the pc board. electrical characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), v in = -0.5dbfs, clktyp = high, dce = high, pd = low, g/ t = low, f clk = 65mhz (50% duty cycle), t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units normal operating mode, f in = 175mhz at -0.5dbfs, clktyp = gnd, single-ended clock 337 normal operating mode, f in = 175mhz at -0.5dbfs, clktyp = ov dd , differential clock 363 406 analog power dissipation p diss power-down mode clock idle, pd = ov dd 0.15 mw normal operating mode, f in = 175mhz at -0.5dbfs, ov dd = 2.0v, c l 5pf 8.2 ma digital output supply current i ovdd power-down mode clock idle, pd = ov dd 20 ? timing characteristics (figure 6) clock pulse-width high t ch 7.7 ns clock pulse-width low t cl 7.7 ns data-valid delay t dav c l = 5pf (note 6) 6.9 ns data setup time before rising edge of dav t setup c l = 5pf (notes 5, 6) 8.5 ns data hold time after rising edge of dav t hold c l = 5pf (notes 5, 6) 6.3 ns wake-up time from power-down t wake v refin = 2.048v 10 ms
MAX12553 14-bit, 65msps, 3.3v adc _______________________________________________________________________________________ 7 single-tone fft plot (8192-point data record) MAX12553 toc01 frequency (mhz) amplitude (dbfs) 24 28 8121620 4 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -120 -110 032 f clk = 65mhz f in = 3.00720215mhz a in = -0.542dbfs snr = 74.223db sinad = 74.147db thd = -91.794dbc sfdr = 91.499dbc hd3 hd2 single-tone fft plot (8192-point data record) MAX12553 toc02 frequency (mhz) amplitude (dbfs) 24 28 8121620 4 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -120 -110 032 f clk = 65mhz f in = 32.39685059mhz a in = -0.469dbfs snr = 74.206db sinad = 73.534db thd = -81.965dbc sfdr = 86.015dbc hd3 hd2 single-tone fft plot (8192-point data record) MAX12553 toc03 frequency (mhz) amplitude (dbfs) 24 28 8121620 4 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -120 -110 032 f clk = 65mhz f in = 69.89562988mhz a in = -0.460dbfs snr = 73.772db sinad = 73.615db thd = -88.110dbc sfdr = 88.325dbc hd3 hd2 single-tone fft plot (8192-point data record) MAX12553 toc04 frequency (mhz) amplitude (dbfs) 24 28 8121620 4 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -120 -110 032 f clk = 65mhz f in = 174.9017334mhz a in = -0.499dbfs snr = 70.971db sinad = 70.260db thd = -78.475dbc sfdr = 80.267dbc hd5 hd2 single-tone fft plot (8192-point data record) MAX12553 toc05 frequency (mhz) amplitude (dbfs) 24 28 8121620 4 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -120 -110 032 f clk = 64.96256mhz f in = 250.00911mhz a in = -0.494dbfs snr = 69.39db sinad = 68.67db thd = -76.8dbc sfdr = 78.6dbc hd2 hd3 two-tone fft plot (16,384-point data record) MAX12553 toc06 frequency (mhz) amplitude (dbfs) 24 28 8121620 4 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -120 -110 032 f clk = 65mhz f in1 = 68.50311279mhz a in1 = -7.018dbfs f in2 = 71.50238037mhz a in2 = -7.087dbfs sfdr tt = 90.085dbc imd = -87.812dbc im3 = -91.844dbc f in1 f in2 2 x f in2 - f in1 two-tone fft plot (16,384-point data record) MAX12553 toc07 frequency (mhz) amplitude (dbfs) 24 28 8121620 4 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -120 -110 032 f clk = 65.00352mhz f in1 = 172.4870625mhz a in1 = -7.047dbfs f in2 = 177.4861125mhz a in2 = -6.984dbfs sfdr tt = 81.484dbc imd = -80.035dbc im3 = -83.511dbc f in1 f in2 2 x f in2 - f in1 f in2 - f in1 f in1 + f in2 integral nonlinearity MAX12553 toc08 digital output code inl (lsb) 12288 8192 4096 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 0 16384 differential nonlinearity MAX12553 toc09 digital output code dnl (lsb) 12288 8192 4096 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 16384 t ypical operating characteristics (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), v in = -0.5dbfs, clktyp = high, dce = high, pd = low, g/ t = low, f clk 65mhz (50% duty cycle), t a = +25?, unless otherwise noted.)
MAX12553 14-bit, 65msps, 3.3v adc 8 _______________________________________________________________________________________ snr, sinad vs. sampling rate MAX12553 toc10 f clk (mhz) snr, sinad (db) 60 40 20 66 67 68 69 70 71 72 73 74 75 65 080 f in 70mhz snr sinad sfdr, -thd vs. sampling rate MAX12553 toc11 f clk (mhz) sfdr, -thd (db) 60 40 20 65 70 75 80 85 90 95 100 60 080 f in 70mhz sfdr -thd power dissipation vs. sampling rate MAX12553 toc12 f clk (mhz) power dissipation (mw) 60 40 20 250 300 350 400 450 500 200 080 differential clock f in 70mhz c l 5pf analog + digital power analog power snr, sinad vs. sampling rate MAX12553 toc13 f clk (mhz) snr, sinad (db) 60 40 20 66 67 68 69 70 71 72 73 74 75 65 080 f in 175mhz snr sinad sfdr, -thd vs. sampling rate MAX12553 toc14 f clk (mhz) sfdr, -thd (db) 60 40 20 65 70 75 80 85 90 95 100 60 080 f in 175mhz sfdr -thd power dissipation vs. sampling rate MAX12553 toc15 f clk (mhz) power dissipation (mw) 60 40 20 250 300 350 400 450 500 200 080 differential clock f in 175mhz c l 5pf analog + digital power analog power snr, sinad vs. analog input frequency MAX12553 toc16 analog input frequency (mhz) snr, sinad (db) 300 200 100 57 59 61 63 65 67 69 71 73 75 55 0 400 f clk 65mhz snr sinad sfdr, -thd vs. analog input frequency MAX12553 toc17 analog input frequency (mhz) sfdr, -thd (dbc) 300 200 100 60 65 70 75 80 85 90 95 55 0 400 f clk 65mhz sfdr -thd power dissipation vs. analog input frequency MAX12553 toc18 analog input frequency (mhz) power dissipation (mw) 300 200 100 250 300 350 400 450 500 200 0 400 analog + digital power analog power differential clock f clk 65mhz c l 5pf t ypical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), v in = -0.5dbfs, clktyp = high, dce = high, pd = low, g/ t = low, f clk 65mhz (50% duty cycle), t a = +25?, unless otherwise noted.)
MAX12553 14-bit, 65msps, 3.3v adc _______________________________________________________________________________________ 9 snr, sinad vs. analog input amplitude MAX12553 toc19 analog input amplitude (dbfs) snr, sinad (db) -5 -10 -20 -15 -30 -25 -35 30 35 40 45 50 55 60 65 70 75 25 -40 0 f clk = 64.96256mhz f in = 175.0071mhz snr sinad sfdr, -thd vs. analog input amplitude MAX12553 toc20 analog input amplitude (dbfs) sfdr, -thd (dbc) -5 -10 -20 -15 -30 -25 -35 40 50 60 70 80 90 100 30 -40 0 f clk = 64.96256mhz f in = 175.0071mhz sfdr -thd power dissipation vs. analog input amplitude MAX12553 toc21 analog input amplitude (dbfs) power dissipation (mw) -5 -10 -20 -15 -30 -25 -35 250 300 350 400 450 500 200 -40 0 differential clock f clk = 64.96256mhz f in = 175.0071mhz c l 5pf analog + digital power analog power snr, sinad vs. analog supply voltage MAX12553 toc22 v dd (v) snr, sinad (db) 3.4 3.0 3.2 2.8 66 67 68 69 70 71 72 73 74 75 65 2.6 3.6 f clk = 64.96256mhz f in = 175.00717mhz snr sinad sfdr, -thd vs. analog supply voltage MAX12553 toc23 v dd (v) sfdr, -thd (dbc) 3.4 3.0 3.2 2.8 65 70 75 80 85 90 95 100 60 2.6 3.6 f clk = 64.96256mhz f in = 175.00717mhz sfdr -thd power dissipation vs. analog supply voltage MAX12553 toc24 v dd (v) power dissipation (mw) 3.4 3.0 3.2 2.8 250 300 350 400 450 500 200 2.6 3.6 differential clock f clk = 64.96256mhz f in = 175.00717mhz c l 5pf analog + digital power analog power snr, sinad vs. digital supply voltage MAX12553 toc25 ov dd (v) snr, sinad (db) 3.4 3.0 2.6 2.2 1.8 66 67 68 69 70 71 72 73 74 75 65 1.4 3.8 f clk = 65mhz f in = 174.9007416mhz snr sinad sfdr, -thd vs. digital supply voltage MAX12553 toc26 ov dd (v) sfdr, -thd (dbc) 3.4 3.0 2.6 2.2 1.8 65 70 75 80 85 90 95 100 60 1.4 3.8 f clk = 65mhz f in = 174.9007416mhz sfdr -thd power dissipation vs. digital supply voltage MAX12553 toc27 ov dd (v) power dissipation (mw) 3.4 3.0 2.6 2.2 1.8 250 300 350 400 450 500 200 1.4 3.8 differential clock f clk = 65mhz f in = 174.9007416mhz c l 5pf analog + digital power analog power t ypical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), v in = -0.5dbfs, clktyp = high, dce = high, pd = low, g/ t = low, f clk 65mhz (50% duty cycle), t a = +25?, unless otherwise noted.)
MAX12553 14-bit, 65msps, 3.3v adc 10 ______________________________________________________________________________________ snr, sinad vs. temperature MAX12553 toc28 temperature ( c) snr, sinad (db) 60 35 10 -15 66 67 68 69 70 71 72 73 74 75 65 -40 85 f clk = 65mhz f in = 175mhz snr sinad sfdr, -thd vs. temperature MAX12553 toc29 temperature ( c) sfdr, -thd (dbc) 60 35 10 -15 72 74 76 78 80 82 84 86 88 90 70 -40 85 f clk = 65mhz f in = 175mhz sfdr -thd analog power dissipation vs. temperature MAX12553 toc30 temperature ( c) analog power dissipation (mw) 60 35 10 -15 250 300 350 400 450 500 200 -40 85 differential clock f clk = 65mhz f in = 175mhz offset error vs. temperature MAX12553 toc31 temperature ( c) offset error (%fs) 60 35 10 -15 -0.2 -0.1 0 0.1 0.2 0.3 -0.3 -40 85 v refin = 2.048v gain error vs. temperature MAX12553 toc32 temperature ( c) gain error (%fs) 60 35 10 -15 -2 -1 0 1 2 3 -3 -40 85 v refin = 2.048v t ypical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), v in = -0.5dbfs, clktyp = high, dce = high, pd = low, g/ t = low, f clk 65mhz (50% duty cycle), t a = +25?, unless otherwise noted.)
MAX12553 14-bit, 65msps, 3.3v adc ______________________________________________________________________________________ 11 reference output voltage load regulation MAX12553 toc33 i refout sink current (ma) v refout (v) 0 -0.5 -1.0 -1.5 1.96 1.97 1.98 1.99 2.00 2.01 2.02 2.03 2.04 2.05 1.95 -2.0 0.5 +85 c +25 c -40 c reference output voltage short-circuit performance MAX12553 toc34 i refout sink current (ma) v refout (v) 0 -1.0 -2.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 -3.0 1.0 +85 c +25 c -40 c reference output voltage vs. temperature MAX12553 toc35 temperature ( c) v refout (v) 60 35 10 -15 2.031 2.033 2.035 2.037 2.039 2.029 -40 85 refp, com, refn load regulation MAX12553 toc36 sink current (ma) voltage (v) 1 0 -1 0.5 1.0 1.5 2.0 2.5 3.0 0 -2 2 v refp v com v refn internal reference mode and buffered external reference mode refp, com, refn short-circuit performace MAX12553 toc37 sink current (ma) voltage (v) 4 0 -4 0.5 1.0 1.5 2.0 2.5 3.5 3.0 0 -8 12 8 v refp v com v refn internal reference mode and buffered external reference mode t ypical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), v in = -0.5dbfs, clktyp = high, dce = high, pd = low, g/ t = low, f clk 65mhz (50% duty cycle), t a = +25?, unless otherwise noted.)
MAX12553 14-bit, 65msps, 3.3v adc 12 ______________________________________________________________________________________ pin name function 1 refp positive reference i/o. the full-scale analog input range is (v refp - v refn ) x 2/3. bypass refp to gnd with a 0.1? capacitor. connect a 1? capacitor in parallel with a 10? capacitor between refp and refn. place the 1? refp to refn capacitor as close to the device as possible on the same side of the pc board. 2 refn negative reference i/o. the full-scale analog input range is (v refp - v refn ) x 2/3. bypass refn to gnd with a 0.1? capacitor. connect a 1? capacitor in parallel with a 10? capacitor between refp and refn. place the 1? refp to refn capacitor as close to the device as possible on the same side of the pc board. 3 com common-mode voltage i/o. bypass com to gnd with a 2.2? capacitor. place the 2.2? com to gnd capacitor as close to the device as possible . this 2.2? capacitor can be placed on the opposite side of the pc board and connected to the MAX12553 through a via. 4, 7, 16, 35 gnd ground. connect all ground pins and ep together. 5 inp positive analog input 6 inn negative analog input 8 dce duty-cycle equalizer input. connect dce low (gnd) to disable the internal duty-cycle equalizer. connect dce high (ov dd or v dd ) to enable the internal duty-cycle equalizer. 9 clkn negative clock input. in differential clock input mode (clktyp = ov dd or v dd ), connect the differential clock signal between clkp and clkn. in single-ended clock mode (clktyp = gnd), apply the single- ended clock signal to clkp and connect clkn to gnd. 10 clkp positive clock input. in differential clock input mode (clktyp = ov dd or v dd ), connect the differential clock signal between clkp and clkn. in single-ended clock mode (clktyp = gnd), apply the single- ended clock signal to clkp and connect clkn to gnd. 11 clktyp clock type definition input. connect clktyp to gnd to define the single-ended clock input. connect clktyp to ov dd or v dd to define the differential clock input. 12?5, 36 v dd analog power input. connect v dd to a 3.15v to 3.60v power supply. bypass v dd to gnd with a parallel capacitor combination of 2.2? and 0.1?. connect all v dd pins to the same potential. 17, 34 ov dd output-driver power input. connect ov dd to a 1.7v to v dd power supply. bypass ov dd to gnd with a parallel capacitor combination of 2.2? and 0.1?. 18 dor data out-of-range indicator. the dor digital output indicates when the analog input voltage is out of range. when dor is high, the analog input is beyond its full-scale range. when dor is low, the analog input is within its full-scale range (figure 6). 19 d13 cmos digital output, bit 13 (msb) 20 d12 cmos digital output, bit 12 21 d11 cmos digital output, bit 11 22 d10 cmos digital output, bit 10 23 d9 cmos digital output, bit 9 24 d8 cmos digital output, bit 8 25 d7 cmos digital output, bit 7 26 d6 cmos digital output, bit 6 27 d5 cmos digital output, bit 5 pin description
MAX12553 14-bit, 65msps, 3.3v adc ______________________________________________________________________________________ 13 pin name function 28 d4 cmos digital output, bit 4 29 d3 cmos digital output, bit 3 30 d2 cmos digital output, bit 2 31 d1 cmos digital output, bit 1 32 d0 cmos digital output, bit 0 (lsb) 33 dav data-valid output. dav is a single-ended version of the input clock that is compensated to correct for any input clock duty-cycle variations. dav is typically used to latch the MAX12553 output data into an external back-end digital circuit. 37 pd power-down input. force pd high for power-down mode. force pd low for normal operation. 38 refout internal reference voltage output. for internal reference operation, connect refout directly to refin or use a resistive divider from refout to set the voltage at refin. bypass refout to gnd with a 0.1? capacitor. 39 refin reference input. in internal reference mode and buffered external reference mode, bypass refin to gnd with a 0.1? capacitor. in these modes,v refp - v refn = v refin x 3/4. for unbuffered external reference mode operation, connect refin to gnd. 40 g/ t output format select input. connect g/ t to gnd for the two? complement digital output format. connect g/ t to ov dd or v dd for the gray code digital output format. ?p exposed paddle. the MAX12553 relies on the exposed paddle connection for a low-inductance ground connection. connect ep to gnd to achieve specified performance. use multiple vias to connect the top-side pc board ground plane to the bottom-side pc board ground plane. pin description (continued) MAX12553 + ? digital error correction flash adc t/h dac stage 2 d13?0 inp inn stage 1 t/h stage 9 stage 10 end of pipe output drivers d13?0 figure 1. pipeline architecture?tage blocks
MAX12553 detailed description the MAX12553 uses a 10-stage, fully differential, pipelined architecture (figure 1) that allows for high- speed conversion while minimizing power consump- tion. samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. from input to output, the total clock-cycle latency is 8.5 clock cycles. each pipeline converter stage converts its input voltage into a digital output code. at every stage, except the last, the error between the input voltage and the digital output code is multiplied and passed along to the next pipeline stage. digital error correction compensates for adc comparator offsets in each pipeline stage and ensures no missing codes. figure 2 shows the MAX12553 functional diagram. input track-and-hold (t/h) circuit figure 3 displays a simplified functional diagram of the input t/h circuit. this input t/h circuit allows for high analog input frequencies of 175mhz and beyond and supports a common-mode input voltage of v dd /2 ?.5v. the MAX12553 sampling clock controls the adc? switched-capacitor t/h architecture (figure 3) allowing the analog input signal to be stored as charge on the sampling capacitors. these switches are closed (track) when the sampling clock is high and open (hold) when the sampling clock is low (figure 4). the analog input signal source must be capable of providing the dynam- ic current necessary to charge and discharge the sam- pling capacitors. to avoid signal degradation, these capacitors must be charged to one-half lsb accuracy within one-half of a clock cycle. the analog input of the MAX12553 supports differential or single-ended input drive. for optimum performance with differential inputs, balance the input impedance of inp and inn and set the common-mode voltage to mid- supply (v dd /2). the MAX12553 provides the optimum common-mode voltage of v dd /2 through the com out- put when operating in internal reference mode and buffered external reference mode. this com output voltage can be used to bias the input network as shown in figures 10, 11, and 12. reference output (refout) an internal bandgap reference is the basis for all the internal voltages and bias currents used in the MAX12553. the power-down logic input (pd) enables and disables the reference circuit. the reference circuit requires 10ms to power up and settle when power is applied to the MAX12553 or when pd transitions from high to low. refout has approximately 17k ? to gnd when the MAX12553 is in power-down. the internal bandgap reference and its buffer generate v refout to be 2.048v. the reference temperature coeffi- cient is typically +50ppm/?. connect an external 0.1? bypass capacitor from refout to gnd for stability. 14-bit, 65msps, 3.3v adc 14 ______________________________________________________________________________________ MAX12553 inp inn 14-bit pipeline adc dec reference system com refout refn refp ov dd dav output drivers d13?0 dor refin t/h power control and bias circuits clkp clock generator and duty-cycle equalizer clkn clktyp pd v dd gnd dce g/t figure 2. simplified functional diagram MAX12553 c par 2pf v dd bond wire inductance 1.5nh inp sampling clock *the effective resistance of the switched sampling capacitors is: *c sample 4.5pf c par 2pf v dd bond wire inductance 1.5nh inn *c sample 4.5pf r sample = 1 f clk x c sample figure 3. simplified input t/h circuit
refout sources up to 1.0ma and sinks up to 0.1ma for external circuits with a load regulation of 35mv/ma. short-circuit protection limits i refout to a 2.1ma source current when shorted to gnd and a 0.24ma sink current when shorted to v dd . analog inputs and reference configurations the MAX12553 full-scale analog input range is adjustable from ?.35v to ?.10v with a common- mode input range of v dd /2 ?.5v. the MAX12553 pro- vides three modes of reference operation. the voltage at refin (v refin ) sets the reference operation mode (table 1). to operate the MAX12553 with the internal reference, connect refout to refin either with a direct short or through a resistive divider. in this mode, com, refp, and refn are low-impedance outputs with v com = v dd /2, v refp = v dd /2 + v refin x 3/8, and v refn = v dd /2 - v refin x 3/8. the refin input impedance is very large (>50m ? ). when driving refin through a resistive divider, use resistances 10k ? to avoid load- ing refout. buffered external reference mode is virtually identical to internal reference mode except that the reference source is derived from an external reference and not the MAX12553 refout. in buffered external reference mode, apply a stable 0.7v to 2.2v source at refin. in this mode, com, refp, and refn are low-impedance outputs with v com = v dd /2, v refp = v dd /2 + v refin x 3/8, and v refn = v dd /2 - v refin x 3/8. to operate the MAX12553 in unbuffered external refer- ence mode, connect refin to gnd. connecting refin to gnd deactivates the on-chip reference buffers for com, refp, and refn. with the respective buffers deactivated, com, refp, and refn become high- impedance inputs and must be driven through sepa- rate, external reference sources. drive v com to v dd /2 ?%, and drive refp and refn such that v com = (v refp + v refn )/2. the full-scale analog input range is ?v refp - v refn ) x 2/3. MAX12553 14-bit, 65msps, 3.3v adc ______________________________________________________________________________________ 15 t ad t/h clkn clkp t aj track hold track hold track hold track hold analog input sampled d ata figure 4. t/h aperture timing v refin reference mode 35% v refout to 100% v refout internal reference mode . drive refin with refout either through a direct short or a resistive divider. the full-scale analog input range is ? refin /2: v com = v dd /2 v refp = v dd /2 + v refin x 3/8 v refn = v dd /2 - v refin x 3/8 0.7v to 2.2v buffered external reference mode . apply an external 0.7v to 2.2v reference voltage to refin. the full-scale analog input range is ? refin /2: v com = v dd /2 v refp = v dd /2 + v refin x 3/8 v refn = v dd /2 - v refin x 3/8 <0.4v unbuffered external reference mode . drive refp, refn, and com with external reference sources. the full-scale analog input range is ?v refp - v refn ) x 2/3. table 1. reference modes
MAX12553 all three modes of reference operation require the same bypass capacitor combinations. bypass com with a 2.2? capacitor to gnd. bypass refp and refn each with a 0.1? capacitor to gnd. bypass refp to refn with a 1? capacitor in parallel with a 10? capacitor. place the 1? capacitor as close to the device as possible on the same side of the pc board . bypass refin and refout to gnd with a 0.1? capacitor. for detailed circuit suggestions, see figure 13 and figure 14. clock input and clock control lines (clkp, clkn, clktyp) the MAX12553 accepts both differential and single- ended clock inputs. for single-ended clock input oper- ation, connect clktyp to gnd, clkn to gnd, and drive clkp with the external single-ended clock signal. for differential clock input operation, connect clktyp to ov dd or v dd , and drive clkp and clkn with the external differential clock signal. to reduce clock jitter, the external single-ended clock must have sharp falling edges. consider the clock input as an analog input and route it away from any other analog inputs and digital signal lines. clkp and clkn are high impedance when the MAX12553 is powered down (figure 5). low clock jitter is required for the specified snr perfor- mance of the MAX12553. analog input sampling occurs on the falling edge of the clock signal, requiring this edge to have the lowest possible jitter. jitter limits the maximum snr performance of any adc according to the following relationship: where f in represents the analog input frequency and t j is the total system clock jitter. clock jitter is especially critical for undersampling applications. for example, assuming that clock jitter is the only noise source, to obtain the specified 71db of snr with an input frequen- cy of 175mhz, the system must have less than 0.25ps of clock jitter. in actuality, there are other noise sources such as thermal noise and quantization noise that con- tribute to the system noise, requiring the clock jitter to be less than 0.2ps to obtain the specified 71db of snr at 175mhz. clock duty-cycle equalizer (dce) the clock duty-cycle equalizer uses a delay-locked loop (dll) to create internal timing signals that are duty-cycle independent. due to this dll, the MAX12553 requires approximately 100 clock cycles to acquire and lock to new clock frequencies. disabling the clock duty-cycle equalizer reduces the analog supply current by 1.5ma. snr ft in j log = ? ? ? ? ? ? 20 1 2 14-bit, 65msps, 3.3v adc 16 ______________________________________________________________________________________ MAX12553 clkp clkn v dd gnd 10k ? 10k ? 10k ? 10k ? duty-cycle equalizer switches s 1_ and s 2_ are open during power-down, making clkp and clkn high impedance. switches s 2_ are open in single-ended clock mode. s 1h s 2h s 1l s 2l figure 5. simplified clock-input circuit
system-timing requirements figure 6 shows the relationship between the clock, ana- log inputs, dav indicator, dor indicator, and the result- ing output data. the analog input is sampled on the falling edge of the clock signal and the resulting data appears at the digital outputs 8.5 clock cycles later. the dav indicator is synchronized with the digital out- put and optimized for use in latching data into digital back-end circuitry. alternatively, digital back-end cir- cuitry can be latched with the falling edge of the con- version clock (clkp-clkn). data-valid output (dav) dav is a single-ended version of the input clock (clkp). output data changes on the falling edge of dav, and dav rises once output data is valid (figure 6). the state of the duty-cycle equalizer input (dce) changes the waveform at dav. with the duty-cycle equalizer disabled (dce = low), the dav signal is the inverse of the signal at clkp delayed by 6.8ns (t dav ). with the duty-cycle equalizer enabled (dce = high), the dav signal has a fixed pulse width that is independent of clkp. in either case, with dce high or low, output data at d13?0 and dor are valid from 8.5ns before the ris- ing edge of dav to 6.3ns after the rising edge of dav, and the rising edge of dav is synchronized to have a 6.9ns (t dav ) delay from the falling edge of clkp. dav is high impedance when the MAX12553 is in power-down (pd = high). dav is capable of sinking and sourcing 600? and has three times the drive strength of d13?0 and dor. dav is typically used to latch the MAX12553 output data into an external back- end digital circuit. keep the capacitive load on dav as low as possible (<25pf) to avoid large digital currents feeding back into the analog portion of the MAX12553 and degrading its dynamic performance. an external buffer on dav isolates it from heavy capacitive loads. refer to the max12555 evaluation kit schematic for an example of dav driving back-end digital circuitry through an exter- nal buffer. MAX12553 14-bit, 65msps, 3.3v adc ______________________________________________________________________________________ 17 dav d13?0 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 t dav t setup t ad n-1 n-2 n-3 t hold t cl t ch dor 8.5 clock-cycle data latency differential analog input (inp?nn) t setup t hold n n+1 n+2 n+3 n+5 n+6 n+7 n-1 n-2 n-3 n+9 n+4 n+8 clkn clkp (v refp - v refn ) x 2/3 (v refn - v refp ) x 2/3 figure 6. system-timing diagram
MAX12553 data out-of-range indicator (dor) the dor digital output indicates when the analog input voltage is out of range. when dor is high, the analog input is out of range. when dor is low, the analog input is within range. the valid differential input range is from (v refp - v refn ) x 3/4 to (v refn - v refp ) x 3/4. signals outside this valid differential range cause dor to assert high as shown in table 2 and figure 6. dor is synchronized with dav and transitions along with the output data d13?0. there is an 8.5 clock- cycle latency in the dor function as is with the output data (figure 6). dor is high impedance when the MAX12553 is in power-down (pd = high). dor enters a high-imped- ance state within 10ns after the rising edge of pd and becomes active 10ns after pd? falling edge. digital output data (d13?0), output format (g/ t ) the MAX12553 provides a 14-bit, parallel, tri-state out- put bus. d13?0 and dor update on the falling edge of dav and are valid on the rising edge of dav. the MAX12553 output data format is either gray code or two? complement, depending on the logic input g/ t . with g/ t high, the output data format is gray code. with g/ t low, the output data format is two? comple- ment. see figure 8 for a binary-to-gray and gray-to- binary code-conversion example. the following equations, table 2, figure 7, and figure 8 define the relationship between the digital output and the analog input: for gray code (g/ t = 1) for two? complement (g/ t = 0) where code 10 is the decimal equivalent of the digital output code as shown in table 2. digital outputs d13?0 are high impedance when the MAX12553 is in power-down (pd = high). d13?0 tran- sition high 10ns after the rising edge of pd and become active 10ns after pd? falling edge. keep the capacitive load on the MAX12553 digital out- puts d13?0 as low as possible (<15pf) to avoid large digital currents feeding back into the analog portion of the MAX12553 and degrading its dynamic perfor- mance. the addition of external digital buffers on the digital outputs isolates the MAX12553 from heavy capacitive loading. to improve the dynamic perfor- mance of the MAX12553, add 220 ? resistors in series with the digital outputs close to the MAX12553. refer to the max12555 evaluation kit schematic for an example of the digital outputs driving a digital buffer through 220 ? series resistors. power-down input (pd) the MAX12553 has two power modes that are con- trolled with the power-down digital input (pd). with pd vv v v code inp inn refp refn ?? = () 4 3 16384 10 vv v v code inp inn refp refn ?? ? = () 4 3 8192 16384 10 14-bit, 65msps, 3.3v adc 18 ______________________________________________________________________________________
MAX12553 14-bit, 65msps, 3.3v adc ______________________________________________________________________________________ 19 gray code output code (g/ t = 1) two?-complement output code (g/ t = 0) binary d13 ? d0 dor hexadecimal equivalent of d13 ? d0 decimal equivalent of d13 ? d0 (code 10 ) binary d13 ? d0 dor hexadecimal equivalent of d13 ? d0 decimal equivalent of d13 ? d0 (code 10 ) v inp - v inn v refp = 2.418v v refn = 0.882v 10 0000 0000 0000 1 0x2000 +16383 01 1111 1111 1111 1 0x1fff +8191 >+1.023875v (data out of range) 10 0000 0000 0000 0 0x2000 +16383 01 1111 1111 1111 0 0x1fff +8191 +1.023875v 10 0000 0000 0001 0 0x2001 +16382 01 1111 1111 1110 0 0x1ffe +8190 +1.023750v 11 0000 0000 0011 0 0x3003 +8194 00 0000 0000 0010 0 0x0002 +2 +0.000250v 11 0000 0000 0001 0 0x3001 +8193 00 0000 0000 0001 0 0x0001 +1 +0.000125v 11 0000 0000 0000 0 0x3000 +8192 00 0000 0000 0000 0 0x0000 0 +0.000000v 01 0000 0000 0000 0 0x1000 +8191 11 1111 1111 1111 0 0x3fff -1 -0.000125v 01 0000 0000 0001 0 0x1001 +8190 11 1111 1111 1110 0 0x3ffe -2 -0.000250v 00 0000 0000 0001 0 0x0001 +1 10 0000 0000 0001 0 0x2001 -8191 -1.023875v 00 0000 0000 0000 0 0x0000 0 10 0000 0000 0000 0 0x2000 -8192 -1.024000v 00 0000 0000 0000 1 0x0000 0 10 0000 0000 0000 1 0x2000 -8192 <-1.024000v (data out of range) () table 2. output codes vs. input voltage
MAX12553 14-bit, 65msps, 3.3v adc 20 ______________________________________________________________________________________ low, the MAX12553 is in normal operating mode. with pd high, the MAX12553 is in power-down mode. the power-down mode allows the MAX12553 to effi- ciently use power by transitioning to a low-power state when conversions are not required. additionally, the MAX12553 parallel output bus is high impedance in power-down mode, allowing other devices on the bus to be accessed. in power-down mode, all internal circuits are off, the analog supply current reduces to 0.045ma, and the digital supply current reduces to 0.02ma. the following list shows the state of the analog inputs and digital out- puts in power-down mode: inp, inn analog inputs are disconnected from the internal input amplifier (figure 3). refout has approximately 17k ? to gnd. refp, com, refn go high impedance with respect to v dd and gnd, but there is an internal 4k ? resistor between refp and com, as well as an internal 4k ? resistor between refn and com. d13?0, dor, and dav go high impedance. clkp, clkn go high impedance (figure 5). the wake-up time from power-down mode is dominat- ed by the time required to charge the capacitors at refp, refn, and com. in internal reference mode and buffered external reference mode, the wake-up time is typically 10ms with the recommended capacitor array (figure 13). when operating in unbuffered external ref- erence mode, the wake-up time is dependent on the external reference drivers. applications information using transformer coupling in general, the MAX12553 provides better sfdr and thd performance with fully differential input signals as opposed to single-ended input drive. in differential input mode, even-order harmonics are lower as both inputs are balanced, and each of the adc inputs only requires half the signal swing compared to single-ended input mode. an rf transformer (figure 10) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the MAX12553 for optimum performance. connecting the center tap of the transformer to com provides a v dd /2 dc level shift to the input. although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. a reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. the configuration of figure 10 is good for frequencies up to nyquist (f clk /2). the circuit of figure 11 converts a single-ended input signal to fully differential just as figure 10. however, figure 11 utilizes an additional transformer to improve differential input voltage (lsb) two's complement output code (lsb) -8189 +8191 +8189 -1 0 +1 -8191 0x2000 0x2001 0x2002 0x2003 0x1fff 0x1ffe 0x1ffd 0x3fff 0x0000 0x0001 (v refp - v refn ) x 2/3 (v refp - v refn ) x 2/3 1 lsb = v refp - v refn 16384 4 3 x figure 7. two? complement transfer function (g/ t = 0) differential input voltage (lsb) gray output code (lsb) +1 +8191 +8189 -1 0 -8191 -8189 0x0000 0x0001 0x0003 0x0002 0x2000 0x2001 0x2003 0x1000 0x3000 0x3001 (v refp - v refn ) x 2/3 (v refp - v refn ) x 2/3 1 lsb = v refp - v refn 16384 4 3 x figure 8. gray code transfer function (g/ t = 1)
MAX12553 14-bit, 65msps, 3.3v adc ______________________________________________________________________________________ 21 binary-to-gray code conversion 1) the most significant gray code bit is the same as the most significant binary bit. 2) subsequent gray code bits are found according to the following equation: binary gray code bit position 3) repeat step 2 until complete. binary gray code bit position 4) the final gray code conversion is: binary bit position gray-to-binary code conversion where is the exclusive or function (see truth t able below) and x is the bit position. 011 101001100 0 d11 d7 d3 d0 1 d13 1 0 01 1 1 0100 1100 0 d11 d7 d3 d0 1 1 0 0 d13 01 1 1 0100 1100 d11 d7 d3 d0 1 0 d13 1011 0100 1100 binary gray code 0 d11 d7 d3 d0 bit position 01 d13 gray code 0 101 10 1110 1010 gray x = binary x binary x+1 gray 12 = binary 12 binary 13 gray 12 = 1 0 gray 12 = 1 gray 11 = binary 11 binary 12 gray 11 = 1 1 gray 11 = 0 1) the most significant binary bit is the same as the most significant gray code bit. 2) subsequent binary bits are found according to the following equation: gray code binary bit position 3) repeat step 2 until complete. gray code binary bit position 4) the final gray code conversion is: gray code bit position where is the exclusive or function (see truth t able below) and x is the bit position. 0 1 00 1110 1010 0 d11 d7 d3 d0 1 0 11 d13 1 1 01 0 1110 1010 0 d11 d7 d3 d0 1 1 d13 01 0 0 1110 1010 d11 d7 d3 d0 1 1 d13 0110 1110 1010 gray code binary 0 d11 d7 d3 d0 bit position 01 d13 binary 0 111 01 0100 1100 binary x = binary x+1 gray x binary 12 = binary 13 gray 12 binary 12 = 0 1 binary 12 = 1 binary 11 = binary 12 gray 11 binary 11 = 1 0 binary 11 = 1 ab 00 01 10 11 0 1 1 0 exculsive or truth table y = a b figure 9. binary-to-gray and gray-to-binary code conversion
MAX12553 14-bit, 65msps, 3.3v adc 22 ______________________________________________________________________________________ the common-mode rejection, allowing high-frequency signals beyond the nyquist frequency. the two sets of termination resistors provide an equivalent 75 ? termi- nation to the signal source. the second set of termina- tion resistors connects to com, providing the correct input common-mode voltage. two 0 ? resistors in series with the analog inputs allow high if input frequencies. these 0 ? resistors can be replaced with low-value resistors to limit the input bandwidth. single-ended, ac-coupled input signal figure 12 shows an ac-coupled, single-ended input application. the max4108 provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. MAX12553 1 2 3 6 5 4 n.c. v in 0.1 f t1 minicircuits tt1-6 or t1-1t 24.9 ? 24.9 ? 12pf 12pf 2.2 f inp com inn figure 10. transformer-coupled input drive for input frequencies up to nyquist MAX12553 1 2 3 6 5 4 n.c. n.c. t2 minicircuits adt1-1wt 1 2 3 6 5 4 n.c. v in 0.1 f t1 minicircuits adt1-1wt 0 ? * 0 ? * 5.6pf 5.6pf 2.2 f inp com inn 110 ? 0.1% 110 ? 0.1% 75 ? 0.5% 75 ? 0.5% *0 ? resistors can be replaced with low-value resistors to limit the bandwidth. figure 11. transformer-coupled input drive for input frequencies beyond nyquist MAX12553 5.6pf 5.6pf 2.2 f inp com inn 24.9 ? 24.9 ? 100 ? 100 ? 0.1 f max4108 v in figure 12. single-ended, ac-coupled input drive
MAX12553 14-bit, 65msps, 3.3v adc ______________________________________________________________________________________ 23 buffered external reference drives multiple adcs the buffered external reference mode allows for more control over the MAX12553 reference voltage and allows multiple converters to use a common reference. the refin input impedance is >50m ? . figure 13 uses the max6029euk21 precision 2.048v reference as a common reference for multiple convert- ers. the 2.048v output of the max6029 passes through a one-pole 10hz lowpass filter to the max4230. the max4230 buffers the 2.048v reference and provides additional 10hz lowpass filtering before its output is applied to the refin input of the MAX12553. MAX12553 note: one front-end reference circuit is capable of sourcing 15ma and sinking 30ma of output current. *place the 1 f refp-to-refn bypass capacitor as close to the device as possible. 16.2k ? 0.1 f 0.1 f 1 f 2 5 2.048v 2.048v +3.3v 1 2 4 1 3 5 47 ? 1.47k ? +3.3v 10 f 6v 330 f 6v +3.3v 2.2 f 2.2 f 0.1 f 1 f* 10 f 0.1 f 0.1 f 0.1 f refp refn com 3 2 1 v dd gnd refin 39 refout 38 MAX12553 +3.3v 2.2 f 2.2 f 0.1 f 1 f* 10 f 0.1 f 0.1 f 0.1 f refp refn com 3 2 1 v dd gnd refin 39 refout 38 max6029euk21 max4230 figure 13. external buffered reference driving multiple adcs
MAX12553 14-bit, 65msps, 3.3v adc 24 ______________________________________________________________________________________ unbuffered external reference drives multiple adcs the unbuffered external reference mode allows for pre- cise control over the MAX12553 reference and allows multiple converters to use a common reference. connecting refin to gnd disables the internal refer- ence, allowing refp, refn, and com to be driven directly by a set of external reference sources. figure 14 uses the max6029euk30 precision 3.000v reference as a common reference for multiple convert- ers. a seven-component resistive divider chain follows the max6029 voltage reference. the 0.47? capacitor along this chain creates a 10hz lowpass filter. three max4230 operational amplifiers buffer taps along this resistor chain providing 2.413v, 1.647v, and 0.880v to the MAX12553? refp, com, refn reference inputs, MAX12553 *place the 1 f refp-to-refn bypass capacitor as close to the device as possible. 0.1 f 0.1 f 5 2.413v +3.3v 1 2 2 4 1 3 5 47 ? 1.47k ? +3.3v 10 f 6v 330 f 6v +3.3v 2.2 f 0.1 f 1 f* 10 f 0.1 f 0.1 f 0.1 f refout refn refin 39 1 2 3 v dd gnd com refp 38 max6029euk30 max4230 0.1 f 0.47 f 1.647v 2 4 1 3 5 47 ? 1.47k ? +3.3v 10 f 6v 330 f 6v max4230 0.1 f 0.880v 2 4 1 3 5 47 ? 1.47k ? +3.3v 10 f 6v 330 f 6v max4230 MAX12553 +3.3v 2.2 f 0.1 f 1 f* 10 f 0.1 f 0.1 f 0.1 f refout refn refin 39 1 2 3 v dd gnd com refp 38 3.000v 20k ? 1% 20k ? 1% 52.3k ? 1% 52.3k ? 1% 20k ? 1% 20k ? 1% 20k ? 1% 0.1 f 2.2 f 2.2 f figure 14. external unbuffered reference driving multiple adcs
MAX12553 14-bit, 65msps, 3.3v adc ______________________________________________________________________________________ 25 respectively. the feedback around the max4230 op amps provides additional 10hz lowpass filtering. the 2.413v and 0.880v reference voltages set the full-scale analog input range to ?.022v = ?v refp - v refn ) x 2/3. a common power source for all active components removes any concern regarding power-supply sequencing when powering up or down. grounding, bypassing, and board layout the MAX12553 requires high-speed board layout design techniques. refer to the max12555 evaluation kit. data sheet for a board layout reference. locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the adc, using surface-mount devices for minimum inductance. bypass v dd to gnd with a 0.1? ceramic capacitor in parallel with a 2.2? ceramic capacitor. bypass ov dd to gnd with a 0.1? ceramic capacitor in parallel with a 2.2? ceramic capacitor. multilayer boards with ample ground and power planes produce the highest level of signal integrity. all MAX12553 gnds and the exposed backside paddle must be connected to the same ground plane. the MAX12553 relies on the exposed backside paddle con- nection for a low-inductance ground connection. use multiple vias to connect the top-side ground to the bot- tom-side ground. isolate the ground plane from any noisy digital system ground planes such as a dsp or output buffer ground. route high-speed digital signal traces away from the sensitive analog traces. keep all signal lines short and free of 90 turns. ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equal- ly. refer to the max12555 evaluation kit data sheet for an example of symmetric input layout. parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. for the MAX12553, this straight line is between the end points of the transfer function, once offset and gain errors have been nullified. inl deviations are measured at every step of the transfer function and the worst-case devia- tion is reported in the electrical characteristics table. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. for the MAX12553, dnl deviations are measured at every step of the transfer function and the worst-case devia- tion is reported in the electrical characteristics table. offset error offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. ideally the midscale MAX12553 transition occurs at 0.5 lsb above mid- scale. the offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point. gain error gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. the slope of the actual transfer function is measured between two data points: positive full scale and negative full scale. ideally, the positive full-scale MAX12553 transition occurs at 1.5 lsbs below positive full scale, and the negative full- scale transition occurs at 0.5 lsb above negative full scale. the gain error is the difference of the measured transition points minus the difference of the ideal transi- tion points. small-signal noise floor (ssnf) small-signal noise floor is the integrated noise and dis- tortion power in the nyquist band for small-signal inputs. the dc offset is excluded from this noise calcu- lation. for this converter, a small signal is defined as a single tone with an amplitude less than -35dbfs. this parameter captures the thermal and quantization noise characteristics of the converter and can be used to help calculate the overall noise figure of a receive channel. go to www.maxim-ic.com for application notes on thermal + quantization noise floor. signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc? reso- lution (n bits): snr [max] = 6.02 n + 1.76 in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spec- tral components to the nyquist frequency excluding the
MAX12553 14-bit, 65msps, 3.3v adc 26 ______________________________________________________________________________________ fundamental, the first six harmonics (hd2?d7), and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms signal to the rms noise plus distortion. rms noise plus distor- tion includes all spectral components to the nyquist fre- quency excluding the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quantization noise only. enob for a full-scale sinusoidal input waveform is computed from: single-tone spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms amplitude of the next-largest spurious component, excluding dc offset. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmon- ics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 7 are the amplitudes of the 2nd- through 7th-order harmonics (hd2?d7). intermodulation distortion (imd) imd is the ratio of the rms sum of the intermodulation products to the rms sum of the two fundamental input tones. this is expressed as: the fundamental input tone amplitudes (v 1 and v 2 ) are at -7dbfs. fourteen intermodulation products (v im _) are used in the MAX12553 imd calculation. the inter- modulation products are the amplitudes of the output spectrum at the following frequencies, where f in1 and f in2 are the fundamental input tone frequencies: second-order intermodulation products: f in1 + f in2 , f in2 - f in1 third-order intermodulation products: 2 x f in1 - f in2 , 2 x f in2 - f in1 , 2 x f in1 + f in2 , 2 x f in2 + f in1 fourth-order intermodulation products: 3 x f in1 - f in2 , 3 x f in2 - f in1 , 3 x f in1 + f in2 , 3 x f in2 + f in1 fifth-order intermodulation products: 3 x f in1 - 2 x f in2 , 3 x f in2 - 2 x f in1 , 3 x f in1 + 2 x f in2 , 3 x f in2 + 2 x f in1 third-order intermodulation (im3) im3 is the total power of the third-order intermodulation products to the nyquist frequency relative to the total input power of the two input tones f in1 and f in2 . the individual input tone levels are at -7dbfs. the third- order intermodulation products are 2 x f in1 - f in2 , 2 x f in2 - f in1 , 2 x f in1 + f in2 , 2 x f in2 + f in1 . two-tone spurious-free dynamic range (sfdr tt ) sfdr tt represents the ratio, expressed in decibels, of the rms amplitude of either input tone to the rms amplitude of the next-largest spurious component in the spectrum, excluding dc offset. this spurious compo- nent can occur anywhere in the spectrum up to nyquist and is usually an intermodulation product or a harmonic. aperture delay the MAX12553 samples data on the falling edge of its sampling clock. in actuality, there is a small delay between the falling edge of the sampling clock and the imd vv v v vv im im im im log ....... = +++ + + ? ? ? ? ? ? ? ? 20 1 2 2 2 13 2 14 2 1 2 2 2 thd vvvvvv v log = +++++ ? ? ? ? ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 6 2 7 2 1 enob sinad . . = ? ? ? ? ? ? ? 176 602
MAX12553 14-bit, 65msps, 3.3v adc ______________________________________________________________________________________ 27 actual sampling instant. aperture delay (t ad ) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (figure 4). aperture jitter figure 4 depicts the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. output noise (n out ) the output noise (n out ) parameter is similar to the ther- mal + quantization noise parameter and is an indication of the adc? overall noise performance. no fundamental input tone is used to test for n out ; inp, inn, and com are connected together and 1024k data points collected. n out is computed by taking the rms value of the collected data points. overdrive recovery time overdrive recovery time is the time required for the adc to recover from an input transient that exceeds the full-scale limits. the MAX12553 specifies overdrive recovery time using an input transient that exceeds the full-scale limits by ?0%. refp 1 refn 2 com 3 gnd 4 inp 5 inn 6 gnd 7 dce 8 clkn 9 clkp 10 d2 30 d3 29 d4 28 d5 27 d6 26 d7 25 d8 24 d9 23 d10 22 d11 21 40 refin 39 refout 38 pd 37 v dd 36 gnd 35 ov dd 34 dav 33 d0 32 d1 31 clktyp 11 v dd 12 v dd 13 v dd 14 v dd 15 gnd 16 ov dd 17 dor 18 d13 19 d12 20 g/t top view MAX12553 exposed paddle (gnd) thin qfn 6mm x 6mm x 0.8mm pin configuration
MAX12553 14-bit, 65msps, 3.3v adc maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 28 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qfn thin 6x6x0.8 .eps e e l l a1 a2 a e/2 e d/2 d e2/2 e2 (ne-1) x e (nd-1) x e e d2/2 d2 b k k l c l c l c l c l e 1 2 21-0141 package outline 36, 40, 48l thin qfn, 6x6x0.8mm l1 l e 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. nd and ne refer to the number of terminals on each d and e side respectively. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 9. drawing conforms to jedec mo220, except for 0.4mm lead pitch package t4866-1. 7. depopulation is possible in a symmetrical fashion. 3. n is the total number of terminals. 2. all dimensions are in millimeters. angles are in degrees. 1. dimensioning & tolerancing conform to asme y14.5m-1994. notes: 10. warpage shall not exceed 0.10 mm. e 2 2 21-0141 package outline 36, 40, 48l thin qfn, 6x6x0.8mm

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